The prior art in path-delay testing dates to 1985, with the definition of a delay model based on path delay faults. This delay model based on path delay faults taught algorithms to generate tests for path-delay faults in combinational logic circuits. Due to the fact that nobody actually produces purely combinational circuits any more, the only way for these algorithms to be applied to a real circuit is essentially to double each memory device in the circuit so that it can store the two patterns (first clock cycle pattern and second clock cycle pattern) required for the path-delay test as completely independent patterns. This would roughly double the size of the memory portion of the circuit (the section 12 of FIG. 1), which no price-competitive manufacturer is willing to do. As a consequence, all these prior combinational logic approaches to path-delay testing remain largely academic exercises which cannot be used in modern integrated circuit design.
Test generation methods that could be applied to path-delay faults in standard scan sequential circuits first began to appear in 1991. These methods were the first to make feasible the path-delay testing of real circuits. Unfortunately, the methods described in all known papers/publications/patents that target standard scan sequential circuits used a simplified logic algebra that did not include hazard-free values. A hazard-free being a logic value that is to remain at the same logic level and is free of any timing glitches. As a consequence, the methods are unable to target robust tests, which means that any tests they generate may be invalidated or incorrect due to timing problems or voltage glitches in other parts of the circuit. In other words, by not using hazard-free values, a time delay fault may be inaccurately detected when a time delay fault really didn't occur or vice versa, an actual time delay fault could go unreported due to a static timing hazard or glitch. A recent testing method claims to be able to generate robust tests for general sequential circuitry, including standard scan sequential circuits. The absence of certain necessary logic values, however, means that this algorithm is defective and may declare a path untestable even when a robust test exists. None of the prior art provides an error-free method for generating robust tests for standard scan sequential circuitry.
Also in the modern integrated circuit industry, the use of the Boolean difference has not been possible in the generation of robust path-delay tests through custom logic blocks whose structure is not specified, due to the fact that any data structure used for Boolean differences requires huge amount of physical memory to represent the Boolean difference data.
Furthermore, in the modern integrated circuit industry, a stuck-at fault simulation methodology is based on the (PPSFP) Parallel-Pattern Single-Fault Propagation method. The PPSFP method has not been applied to general sequential circuits, due to the intrinsic inefficiencies encountered in simulating sequential devices and feedback loops across multiple clock cycles in such circuits. Thus, when applying the PPSFP method for fault simulation testing, combinational circuits are used for the test simulation.
However, the usual PPSFP method cannot be used for delay fault testing, due to the fact that the PPSFP method assumes the independence of each pattern and that circuit activity ceases when a single pattern has been processed. Since all delay tests are multi-pattern tests, any application of the standard PPSFP method to the simulation of such tests would be non-functional. Furthermore, in a standard scan path testing environment, a second test vector comes from the functionality of the circuit rather than being directly and independently loaded from an external source.
Current simulators for delay faults are built on either a PPSFP with the added assumption of an enhanced scan design methodology, rendering them incapable of being used for a standard scan design environment, or concurrent fault simulators for general sequential logic, which renders them very inefficient compared to PPSFP methods. Furthermore, current simulators lack the ability to support multiple clock cycles and hazard free value testing, thus a path-delay test verification process in a standard scan design environment cannot be accomplished.
Also, the generation of test vectors to circuit path delay testing can be a complex matter. Therefore, the code used to generate the test vector may have a "bug" or be erroneous and generate a vector which may not function properly to test a path. Therefore, a need exists to both generate a test vector using a first method and verify the correctness of the test vector using a second method wherein errors in the first method are not likely to occur again in the second method.